1. Technical Field
The present invention relates to a semiconductor apparatus, and more particularly, to pumping voltage generation in a semiconductor apparatus.
2. Related Art
A semiconductor apparatus typically boosts an external voltage applied as power, generates high voltages, and uses the generated high voltages in internal circuits. The semiconductor apparatus has a voltage pumping circuit for this purpose to generate the high voltages from the external voltage. The high voltages generated by the pumping circuit are referred to as pumping voltages.
FIG. 1 is a diagram schematically illustrating the configuration of a conventional pumping circuit. Referring to FIG. 1, a conventional pumping circuit includes a voltage detection unit 10, an oscillator 20, a split unit 30, and a voltage pump 40. The voltage detection unit 10 compares the levels of a pumping voltage VPP with a reference voltage Vref and generates an enable signal OSCEN. The oscillator 20 generates a period signal OSCPRE when the enable signal OSCEN is enabled. The split unit 30 splits the period signal OSCPRE into a plurality of pump control signals OSC<1:n>. The voltage pump 40 includes a plurality of pumps and performs a pumping operation in response to the plurality of pump control signals OSC<1:n> generated by the split unit 30. When the level of the pumping voltage VPP becomes lower than the level of the to reference voltage Vref in the pumping circuit configured as described above, the level of the pumping voltage VPP is raised through a pumping operation until the pumping voltage VPP reaches a target voltage level.
FIG. 2 schematically illustrates the pumping circuit shown in FIG. 1 which is applied to a multi-chip semiconductor apparatus. Referring to FIG. 2, the multi-chip semiconductor apparatus comprises first to eighth chips c1-c8 which are stacked to constitute the single semiconductor memory apparatus. As illustrated in FIG. 2, each of the first to eighth chips c1-c8 has its own pumping circuit as shown in FIG. 1. If the level of a pumping voltage VPP becomes lower than a target voltage level, each of the first to eighth chips c1-c8 raises the level of its pumping voltage VPP through the pumping circuit contained in its own chip. The pumping voltage VPP is shared by the respective chips through wires or through-silicon vias (TSVs).
FIG. 3 is a timing diagram illustrating operations of the semiconductor apparatus shown in FIG. 2. As illustrated in FIG. 3, if the level of the pumping voltage VPP becomes lower than the level of a reference voltage Vref and an enable signal OSCEN is enabled, the pumps of the first to eighth chips c1-c8 simultaneously operate in response to a plurality of pump control signals OSC<1:n>_c1 through OSC<1:n>_c8. In FIG. 3, as the enable signal OSCEN is enabled, one pump among the pumps constituting voltage pumps 14, 24, . . . 84 in the first to eighth chips c1-c8 can simultaneously operate in response to pump control signals OSC<1>_c1 through OSC<1>_c8, and two pumps among the pumps constituting the voltage pumps 14, 24, . . . 84 of the first to eighth chips c1-c8 can simultaneously operate in response to pump control signals OSC<1>_c1 through OSC<1>_c8 and OSC<2>_c1 through OSC<2>_c8. In this regard, if the pumps of the first to eighth chips c1-c8 operate simultaneously, the level of the generated pumping voltage VPP may significantly exceed the target voltage level. Also, even though the pumping voltage is shared through the wires, all the chips should be equipped with circuits to detect the level of the pumping voltage VPP.